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INTEGRATED CIRCUITS
PCK2010R CK98R (100/133MHz) RCC spread spectrum system clock generator
Product specification 1999 Oct 19
Philips Semiconductors
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
FEATURES
* Mixed 2.5 V and 3.3 V operation * Four CPU clocks at 2.5 V * Eight PCI clocks at 3.3 V, one free-running
(synchronous with CPU clocks)
Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW.
PIN CONFIGURATION
VSS 1 REF0 REF1 VDD3V XTAL_IN XTAL_OUT 2 3 4 5 6 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD25V APIC2 APIC1 APIC0 VSS VDD25V CPUDIV2_1 CPUDIV2_0 VSS VDD25V CPUCLK3 CPUCLK2 VSS VDD25V CPUCLK1 CPUCLK0 VSS VDD3V VSS PCISTOP CPUSTOP PWRDWN SPREAD SEL1 SEL0 VDD3V 48MHz_USB VSS
* Four 3.3 V fixed clocks @ 66 MHz * Two 2.5 V CPUDIV2 clocks @ 1/2 CPU clock frequency * Three 2.5 V IOAPIC clocks @ 16.67 MHz * One 3.3 V 48 MHz USB clock * Two 3.3 V reference clocks @ 14.318 MHz * Reference 14.31818 MHz Xtal oscillator input * 133 MHz or 100 MHz operation * Power management control input pins * CPU clock jitter 250 ps cycle-cycle * CPU clock skew 175 ps pin-pin * 0.0ns - 1.5 ns CPU - 3V66 delay * 1.5ns - 3.5 ns 3V66 - PCI delay * 1.5ns - 4.0 ns CPU - IOAPIC delay * 1.5ns - 4.0 ns CPU - PCI delay * Available in 56-pin SSOP package * 0.5% center spread spectrum capability via select pins * -0.5% down spread spectrum capability via select pins
DESCRIPTION
The PCK2010R is a clock generator (frequency synthesizer) chip for a Pentium II and other similar processors. The PCK2010R has four CPU clock outputs at 2.5 V, two CPUDIV2 clock outputs running at 1/2 CPU clock frequency (66 MHz or 50 MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33 MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet Intel's drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW.
VSS 7 PCICLK_F PCICLK1 8 9
VDD3V 10 PCICLK2 11 PCICLK3 12 VSS 13 PCICLK4 14 PCICLK5 15 VDD3V 16 PCICLK6 17 PCICLK7 18 VSS 19 VSS 20 3V66_0 21 3V66_1 22 VDD3V 23 VSS 24 3V66_0 25 3V66_1 26 VDD3V 27 SEl133/100 28
SW00504
ORDERING INFORMATION
PACKAGES 56-Pin plastic SSOP TEMPERATURE RANGE 0C to +70C ORDER CODE PCK2010R DL DRAWING NUMBER SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
1999 Oct 19
2
853-2179 22543
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
PIN DESCRIPTION
PIN NUMBER 2,3 5 6 8 9, 11, 12, 14, 15, 17, 18 21, 22, 25, 26 28 30 32, 33 34 35 36 37 41, 42, 45, 46 49, 50 53, 54, 55 4, 10, 16, 23, 27, 31, 39 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 43, 47, 51, 56 SYMBOL REF [0-1] XTAL_IN XTAL_OUT PCICLK_F PCICLK [1-7] 3V66 [0-3] SEL133/100 48 MHz USB SEL [0-1] SPREAD PWRDWN CPUSTOP PCISTOP CPUCLK [0-3] CPUDIV_2 [0-1] IOAPIC [0-2] VDD3V VSS VDD25V 3.3 V 14.318 MHz clock output 14.318 MHz crystal input 14.318 MHz crystal output 3.3 V free running PCI clock 3.3 V PCI clock outputs 3.3 V fixed 66 MHz clock outputs Select input pin for enabling 133 MHz or 100 MHz CPU outputs. H = 133 MHz, L = 100 MHz 3.3 V fixed 48 MHZ clock output Logic select pins. TTL levels. 3.3 V LVTTL input. Enables spread spectrum mode when held LOW. 3.3 V LVTTL input. Device enters powerdown mode when held LOW. 3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2 output remains on all the time. 3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW. 2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100. 2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on state of input pin SEL133/100. 2.5 V clock outputs running divide synchronous with the CPU clock frequency. Fixed 16.67 MHz limit. 3.3 V power supply. Ground 2.5 V power supply FUNCTION
NOTE: 1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5 V supply, all remaining VDD pins tied to a common 3.3 V supply and all VSS pins being common.
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
BLOCK DIAGRAM
LOGIC
PWRDWN LOGIC XTAL_IN X 14.318 MHZ OSC USBPLL
X REF [0-1](14.318 MHz)
XTAL_OUT X
PWRDWN LOGIC
X 48 MHz USB
SPREAD X
SYSPLL
STOP LOGIC
X CPUCLK [0-3]
SEL133/100 SEL0 SEL1 DECODE LOGIC
STOP LOGIC
X 3V66 [0-3] (66MHz)
PWRDWN LOGIC
X CPUDIV2 [0-1]
PWRDWN LOGIC
X PCICLK_F (33MHz)
STOP LOGIC PCISTOP X CPUSTOP X PWRDWN X PWRDWN LOGIC
X PCICLK [1-7] (33 MHz)
X APIC [0-2] (16.67 MHz)
SW00505
1999 Oct 19
4
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
FUNCTION TABLE
SEL 133/100 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CPU HI-Z N/A 100 MHz 100 MHz TCLK/2 N/A 133 MHz 133 MHz CPUDIV2 HI-Z N/A 50 MHz 50 MHz TCLK/4 N/A 66 MHz 66 MHz 3V66 HI-Z N/A 66 MHz 66 MHz TCLK/4 N/A 66 MHz 66 MHz PCI HI-Z N/A 33 MHz 33 MHz TCLK/8 N/A 33 MHz 33 MHz 48 MHz HI-Z N/A HI-Z 48 MHz TCLK/2 N/A HI-Z 48 MHz REF HI-Z N/A 14.318 MHz 14.318 MHz TCLK N/A 14.318 MHz 14.318 MHz IOAPIC HI-Z N/A 16.67 MHz 16.67 MHz TCLK/16 N/A 16.67 MHz 16.67 MHz NOTES 1 2 3 4, 7, 8 5, 6 2 3 4, 7, 8
NOTES: 1. Required for board level "bed-of-nails" testing. 2. Used to support Intel confidential application. 3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state. 4. "Normal" mode of operation. 5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic. 6. Required for DC output impedance verification. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. 8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz CLOCK OUTPUT USBCLK7 TARGET FREQUENCY (MHz) 48.0 ACTUAL FREQUENCY (MHz) 48.008 PPM 167
CLOCK ENABLE CONFIGURATION
CPUSTOP X 0 0 1 1 PWRDWN 0 1 1 1 1 PCISTOP X 0 1 0 1 CPUCLK LOW LOW LOW ON ON CPUDIV2 LOW ON ON ON ON APIC LOW ON ON ON ON 3V66 LOW LOW LOW ON ON PCI LOW LOW ON LOW ON PCI_F LOW ON ON ON ON REF / 48 MHz LOW ON ON ON ON OSC OFF ON ON ON ON VCOs OFF ON ON ON ON
NOTES: 1. LOW means outputs held static LOW as per latency requirement below 2. ON means active. 3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW. 5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
SIGNAL CPUSTOP PCISTOP PWRDWN SIGNAL STATE 0 (DISABLED) 1 (ENABLED) 0 (DISABLED) 1 (ENABLED) 1 (NORMAL OPERATION) 0 (POWER DOWN) LATENCY NO. OF RISING EDGES OF FREE RUNNING PCICLK 1 1 1 1 3 ms 2 MAX
NOTES: 1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the first valid clock that comes out of the device. 2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0 V) SYMBOL VDD3 VDDQ3 VDDQ2 IIK VI IOK VO IO TSTG PTOT PARAMETER DC 3.3 V core supply voltage DC 3.3 V I/O supply voltage DC 2.5 V I/O supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range: -40 to +125C above +55C derate linearly with 11.3mW/K VI < 0 Note 2 VO > VCC or VO < 0 Note 2 VO = 0 to VCC -65 -0.5 -0.5 CONDITION LIMITS MIN -0.5 -0.5 -0.5 MAX +4.6 +4.6 +3.6 -50 5.5 50 VCC + 0.5 50 +150 850 UNIT V V V mA V mA V mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD3V VDD25V PARAMETER DC 3.3 V core supply voltage DC 2.5 V I/O supply voltage Capacitive load on: CPUCLK PCICLK CPUDIV2 3V66 48 MHz clock USB REF IOAPIC DC input voltage range DC output voltage range Reference frequency, oscillator nominal value Operating ambient temperature range in free air 1 device load, possible 2 loads Must meet PCI 2.1 requirements 1 device load, possible 2 loads 1 device load, possible 2 loads 1 device load 1 device load 1 device load CONDITIONS LIMITS MIN 3.135 2.375 10 10 10 10 10 10 10 0 0 14.31818 0 MAX 3.465 2.625 20 30 20 30 20 20 20 VDD3V VDD25V VDD3V 14.31818 +70 UNIT V V pF pF pF pF pF pF pF V V MHz C
CL
VI VO fREF Tamb
POWER MANAGEMENT
CK133 CONDITION Power-down mode (PWRDWN = 0) Full active 100 MHz SEL133/100# = 0 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 Full active 133 MHz SEL133/100# = 1 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 MAXIMUM 2.5V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V = 2.625 V ALL STATIC INPUTS = VDD3V OR VSS 100 A MAXIMUM 3.3V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V= 3.465 V ALL STATIC INPUTS = VDD3V OR VSS 200 A
80 mA
160 mA
90 mA
160 mA
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
DC CHARACTERISTICS
TEST CONDITIONS SYMBOL PARAMETER VDD (V) VIH VIL VOH2 VOL2 VOH3 VOL3 VOH3 VOL3 IO OH IO OH IO OH IO OL IO OL IO OL II IOZ Cin Cxtal Cout HIGH level input voltage LOW level input voltage 2.5 V output HIGH voltage CPUCLK, IOAPIC, CPUDIV2 2.5 V output LOW voltage CPUCLK, IOAPIC, CPUDIV2 3.3 V output HIGH voltage REF, 48 MHz USB 3.3 V output LOW voltage REF, 48 MHz USB 3.3 V output HIGH voltage PCI, 3V66 3.3 V output LOW voltage PCI, 3V66 CPUCLK output HIGH current 48 MHz USB, REF , output HIGH current PCI, 3V66 , output HIGH current CPUCLK output LOW current 48 MHz USB, REF , output LOW current PCI, 3V66 , output LOW current Input leakage current 3-State output OFF-State current Input pin capacitance Xtal pin capacitance, as seen by external crystal Output pin capacitance 18 6 3.135 to 3.465 3.135 to 3.465 2.375 to 2.625 2.375 to 2.625 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 2.375 2.625 3.135 3.465 3.135 3.465 2.375 2.625 3.135 3.465 3.135 3.465 3.465 3.465 VOUT = Vdd or GND IO = 0 IOH = -1 mA IOL = 1 mA IOH = -1 mA IOL = 1 mA IOH = -1 mA IOL= 1 mA VOUT = 1.0 V VOUT = 2.375 V VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.2 V VOUT = 0.3 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.95 V VOUT = 0.4 V OTHER VDD25V = 2.5 V 5% VDD3V = 3.3 V 5% LIMITS Tamb = 0C to +70C MIN 2.0 VSS - 0.3 2.0 - 2.0 - 2.4 - -27 - -29 - -33 - 27 - 29 - 30 - - - TYP MAX VDD + 0.3 0.8 - 0.4 - 0.4 - 0.55 - -27 - -23 - -33 - 30 - 27 - 38 5 10 5 V V V V V V V V mA mA mA mA mA mA A A pF pF pF UNIT
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
AC CHARACTERISTICS
VDD3V = 3.3 V 5%; VDDAPIC = VDD25V = 2.5 V 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0-3) (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW CPUCLK period CPUCLK HIGH time CPUCLK LOW time CPUCLK rise time CPUCLK fall time CPUCLK cycle-cycle jitter Output Duty Cycle CPUCLK pin-pin skew 45 7.5 1.87 1.67 0.4 0.4 MAX 8.0 n/a n/a 1.6 1.6 250 55 175 45 LIMITS Tamb = 0C to +70C 100 MHz MODE MIN 10.0 3.0 2.8 0.4 0.4 MAX 10.5 n/a n/a 1.6 1.6 250 55 175 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES
CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0-1) (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW CPUDIV2 CLK period CPUDIV2 CLK HIGH time CPUDIV2 CLK LOW time CPUDIV2 CLK rise time CPUDIV2 CLK fall time CPUDIV2 CLK cycle-cycle jitter CPUDIV2 CLK Duty Cycle CPUDIV2 CLK pin-pin skew 45 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 250 55 175 45 LIMITS Tamb = 0C to +70C 100 MHz MODE MIN 20.0 7.5 7.3 0.4 0.4 MAX 21.0 n/a n/a 1.6 1.6 250 55 175 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES
PCI CLOCK OUTPUTS, PCI(0-7) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW PCICLK period PCICLK HIGH time PCICLK LOW time PCICLK rise time PCICLK fall time PCICLK cycle-cycle jitter PCICLK Duty Cycle PCICLK pin-pin skew 45 30.0 12.0 12.0 0.5 0.5 MAX n/a n/a n/a 2.0 2.0 500 55 500 45 LIMITS Tamb = 0C to +70C 100 MHz MODE MIN 30.0 12.0 12.0 0.5 0.5 MAX n/a n/a n/a 2.0 2.0 500 55 500 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
APIC(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW IOAPIC CLK period IOAPIC CLK HIGH time IOAPIC CLK LOW time IOAPIC CLK rise time IOAPIC CLK fall time IOAPIC CLK cycle-cycle jitter IOAPIC CLK Duty Cycle IOAPIC CLK pin-pin skew 45 60.0 25.5 25.3 0.4 0.4 MAX 64.0 n/a n/a 1.6 1.6 500 55 250 45 LIMITS Tamb = 0C to +70C 100 MHz MODE MIN 60.0 25.5 25.3 0.4 0.4 MAX 64.0 n/a n/a 1.6 1.6 500 55 250 ns ns ns ns ns ps % ps 1 2 2, 9 5, 10 6, 10 8 8 UNIT NOTES
3V66 CLOCK OUTPUT, 3V66 (0-3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN THKP THKH THKL THRISE THFALL TJITTER DUTY CYCLE THSKW 3V66 CLK period 3V66 CLK HIGH time 3V66 CLK LOW time 3V66 CLK rise time 3V66 CLK fall time 3V66 CLK cycle-cycle jitter 3V66 CLK Duty Cycle 3V66 CLK pin-pin skew 45 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 500 55 250 45 LIMITS Tamb = 0C to +70C 100 MHz MODE MIN 15.0 5.25 5.05 0.4 0.4 MAX 16.0 n/a n/a 1.6 1.6 500 55 250 ns ns ns ns ns ps % ps 1 2 2, 9, 4 5, 10 6, 10 8 8 UNIT NOTES
48MHZ(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER TEST CONDITIONS NOTES f fD THRISE (tR) THFALL (tF) DUTY CYCLE (tD) TJITTER Frequency, Actual Deviation from 48 MHz Output rise edge rate Output fall edge rate Duty Cycle 133 MHz CLK cycle-cycle jitter MIN MAX 500 THSTB (fST) Frequency stabilization from Power-up (cold start) NOTE: 1. See Figure 5 for measure points. Determined by PLL divider ratio (48.008 - 48)/48 1 1 45 100 MHz MIN MAX 500 3 ms ps LIMITS Tamb = 0C to +70C MIN 48.008 +167 4 4 55 MAX MHz ppm ns ns % UNIT
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
AC CHARACTERISTICS (Continued)
TEST CONDITIONS SYMBOL PARAMETER Measurement loads (lumped) CPU@20 pF, 3V66@30 pF 3V66@30 pF, PCI@30 pF CPU@20 pF, IOAPIC@20 pF CPU@20 pF PCI@30 pF CPUDIV2@20 pF CPU@20 pF Measure points CPU@1.25 V, 3V66@1.5 V 3V66@1.5 V, PCI@1.5 V 3CPU@1.25 V, IOAPIC@1.25 V CPU@1.25 V PCI@1.5 V CPUDIV2@ CPU@1.25 V LIMITS Tamb = 0C to +70C MIN 0.0 1.5 1.5 1.5 0.0 TYP 0.45 2.0 2.4 3.8 1.6 MAX 1.5 3.5 4.0 4.0 2.5 ns ns ns ns ns 1 1 1 UNIT NOTES
THPOFFSET THPOFFSET THPOFFSET THPOFFSET THPOFFSET
CPUCLK to 3V66 CLK, CPU leads 3V66 CLK to PCICLK, 3V66 leads CPUCLK to IOAPIC, CPU leads CPUCLK to PCICLK , CPU leads CPUDIV2 to CPUCLK, CPUDIV2 leads
NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks. 3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100 MHz. 4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100 MHz. 5. THKH is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4. 6. THKL is measured at 0.4 V for all outputs as shown in Figure 4. 7. The time is specified from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 s period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Output (see Figure 5 for measure points).
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
SPREAD SPECTRUM FUNCTION TABLE
SPREAD# pin 34 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 0 (active) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) 1 (inactive) SEL133/100# pin 28 0 (100 MHz) 0 (100 MHz) 0 (100 MHz) 0 (100 MHz) 1 (133 MHz) 1 (133 MHz) 1 (133 MHz) 1 (133 MHz) 0 (100 MHz) 0 (100 MHz) 0 (100 MHz) 0 (100 MHz) 1 (133 MHz) 1 (133 MHz) 1 (133 MHz) 1 (133 MHz) SEL1 pin 33 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 pin 32 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3-State to High Impedance 100 MHz, Center Spread 0.5% 100 MHz, Down Spread - 0.5% 100 MHz, Down Spread - 0.5% Test Mode 133 MHz, Center Spread 0.5% 133 MHz, Down Spread - 0.5% 133 MHz, Down Spread - 0.5% 3-State to High Impedance 100 MHz, No Center Spread 0.5% 100 MHz, No Down Spread - 0.5% 100 MHz, No Down Spread - 0.5% Test Mode 133 MHz, No Center Spread 0.5% 133 MHz, No Down Spread - 0.5% 133 MHz, No Down Spread - 0.5% Function F nction 48 MHz PLL Inactive Active Inactive Active Active Active Inactive Active Inactive Active Inactive Active Active Active Inactive Active
1999 Oct 19
11
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
AC WAVEFORMS
VM = 1.25 V @ VDDQ2 and 1.5 V @ VDDQ3 VX = VOL + 0.3 V VY = VOH -0.3 V VOL and VOH are the typical output voltage drop that occur with the output load.
1999 Oct 19
12
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
VDDQ2 CPUCLK @133MHz 1.25V VSS
VDDQ3 3v66 @66MHz 1.5V VSS CPU leads 3V66 THPOFFSET
SW00354
Figure 1. CPUCLK to 3V66 offset
VDDQ3 3V66 @ 66MHz 1.5V VSS
VDDQ3 PCICLK @ 33MHz 1.5V VSS
3V66 leads PCICLK
THPOFFSET
SW00356
Figure 2. 3V66 to PCI offset
VDDQ2 CPUCLK @ 133MHz 1.25V VSS
VDDQ2 IOAPIC @ 16.6MHz 1.25V VSS CPUCLK leads IOAPIC THPOFFSET
SW00357
Figure 3. CPU to IOAPIC offset
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
THKP DUTY CYCLE THKH 2.5V CLOCKING INTERFACE 2.0 1.25 0.4 THKL TRISE TFALL TPKP TPKH 3.3V CLOCKING INTERFACE (TTL) 2.4 1.5 0.4 TPKL TRISE TFALL
SW00242
Figure 4. 2.5V/3.3V clock waveforms
COMPONENT MEASUREMENT POINTS
2.5VOLT MEASURE POINTS VOH = 2.0V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS
VOL = 0.4V VSS
COMPONENT MEASUREMENT POINTS
3.3VOLT MEASURE POINTS VOH = 2.4V VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V SYSTEM MEASUREMENT POINTS
VOL = 0.4V VSS
SW00243
Figure 5. Component versus system measure points
VI SEL133/100, SEL1, SEL0 GND VM
tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS outputs enabled VY
tPZL
VM VX
tPZH
VM
outputs disabled
outputs enabled
SW00454
1999 Oct 19
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Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
Figure 6. 3-State enable and disable times
S1 VDD 2RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT
SW00238
Figure 7. Load circuitry for switching times
PWRDWN
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
CPUCLK (EXTERNAL)
PCICLK (EXTERNAL)
OSC & VCO
USB (48MHz)
Figure 8. Power Management
1999 Oct 19
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A A A A
SW00244
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1999 Oct 19
16
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
NOTES
1999 Oct 19
17
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum system clock generator
PCK2010R
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 10-99 Document order number: 9397-750-06509
Philips Semiconductors
1999 Oct 19 18

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